PIA RAtio
please help me calculte ratio
Time Interest Earned ratio =Earning before Interest & Tax / Interest Expense
EBIT= Interest Expense+ Profit before tax
here what is interest expense?
Operating Income Margin= Operating Profit/ Sales
what is operating profit
Dividend per share= Dividend/ No of shares issued
what is dividend
please guide me
Particular 2007 2008 2009
Revenue – net 70,480,734 89,201,567 94,563,765
COST OF SERVICE
Aircraft fuel 30,315,159 45,854,357 (31,371,753)
Others 36,241,336 39,707,920 (47,257,674)
66,556,495 85,562,277 (78,629,427)
GROSS PROFIT 3,924,239 3,639,290 15,934,338
Distribution costs 4,448,674 5,389,632 (5,911,946)
Administrative expenses 5,256,700 5,818,218 (7,180,665)
Other provisions and adjustment – net 433,223 1,521,179 (689,849)
Exchange loss - net 720,151 24,118,823 (6,711,336)
Other operating income (999,433) (1,830,920) 494,462
9,859,315 35,016,932 (19,999,334)
LOSS FROM OPERATIONS 5,935,076 31,377,642 (4,064,996)
Finance costs 7,135,845 8,351,648 (9,243,768)
LOSS BEFORE TAXATION 13,070,921 39,729,290 (13,308,764)
Taxation 327,785 (3,849,133) 7,486,33
LOSS FOR THE YEAR 13,398,706 35,880,157 (5,822,431)
Particular 2007 2008 2009
Revenue – net 70,480,734 89,201,567 94,563,765
COST OF SERVICE
Aircraft fuel 30,315,159 45,854,357 (31,371,753)
Others 36,241,336 39,707,920 (47,257,674)
66,556,495 85,562,277 (78,629,427)
GROSS PROFIT 3,924,239 3,639,290 15,934,338
Distribution costs 4,448,674 5,389,632 (5,911,946)
Administrative expenses 5,256,700 5,818,218 (7,180,665)
Other provisions and adjustment – net 433,223 1,521,179 (689,849)
Exchange loss - net 720,151 24,118,823 (6,711,336)
Other operating income (999,433) (1,830,920) 494,462
9,859,315 35,016,932 (19,999,334)
LOSS FROM OPERATIONS 5,935,076 31,377,642 (4,064,996)
Finance costs 7,135,845 8,351,648 (9,243,768)
LOSS BEFORE TAXATION 13,070,921 39,729,290 (13,308,764)
Taxation 327,785 (3,849,133) 7,486,33
LOSS FOR THE YEAR 13,398,706 35,880,157 (5,822,431)
--This link and material can help a lot.Applications of Asynchronous Digital Logic
Every Digital Electronics engineer prefers synchronous logic due to many well known reasons. But there are some exceptional cases where asynchronous logic offers best solution compared to synchronous digital logic. These exceptions, however, must be designed with extreme caution and only as a last resort when a synchronous solution cannot be found.
Asynchronous Reset
There are times when an asynchronous reset is acceptable, or even preferred. If the vendor's library includes asynchronously resettable flip-flops, the reset input can be tied to a master reset in order to reduce the routing congestion and to reduce the logic required for a synchronous reset. FPGAs and CPLDs will typically have master reset signals built into the architecture. Using these signals to reset state machines frees up interconnect for other uses.
Asynchronous reset should be used only for resetting the entire chip and should not occur during normal functioning of the chip. After reset, you must ensure that the chip is in a stable state such that no flip-flops will change until an input changes. You must also ensure that the inputs to the chip are stable and will not change for at least one clock cycle after the reset is removed.
Asynchronous Latches on Inputs
Some buses, such as the VME bus, are designed to be asynchronous. In order to interface with these buses, it is necessary to use asynchronous latches to capture addresses or data. Once the data is captured, it must be synchronized to the internal clock. However, it is usually much more efficient to use asynchronous latches to capture the data initially. Unless your chip uses a clock which has a frequency much higher than that of the bus, attempting to synchronously latch these signals will cause a large amount of overhead and may actually produce timing problems rather than reduce them.
Other Asynchronous Circuits
Occasionally, circuits are needed to operate before a clock has started running or when a clock has stopped running. Circuits that generate system resets, and watchdog circuits are examples of these. Every attempt should be made to design these circuits synchronously or move them off chip and use discrete chips whose worst case and best case timing is very explicitly defined. If this cannot be done, design these circuits with care and realize that changes to the semiconductor process may make your chip unusable.
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